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This is mostly a maintenance update that brings the compressor inline with the recently published Khronos Data Format Specification 1.4 release which clarified some ambiguity in the specification. This update also gives minor codec optimizations, bug fixes, and image quality improvements. The biggest improvement for Godot is that builds using MSVC cl.exe will now correctly default to the SSE2-optimized backend rather than the reference C backend. This makes compression more than 3 times faster. Builds using other compilers (GCC, LLVM/Clang) were not impacted by the underlying issue, and see no performance uplift.
1122 lines
25 KiB
C++
1122 lines
25 KiB
C++
// SPDX-License-Identifier: Apache-2.0
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// ----------------------------------------------------------------------------
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// Copyright 2019-2024 Arm Limited
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//
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// Licensed under the Apache License, Version 2.0 (the "License"); you may not
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// use this file except in compliance with the License. You may obtain a copy
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// of the License at:
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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// ----------------------------------------------------------------------------
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/**
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* @brief 4x32-bit vectors, implemented using Armv8-A NEON.
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*
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* This module implements 4-wide 32-bit float, int, and mask vectors for
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* Armv8-A NEON.
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*
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* There is a baseline level of functionality provided by all vector widths and
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* implementations. This is implemented using identical function signatures,
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* modulo data type, so we can use them as substitutable implementations in VLA
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* code.
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*
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* The 4-wide vectors are also used as a fixed-width type, and significantly
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* extend the functionality above that available to VLA code.
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*/
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#ifndef ASTC_VECMATHLIB_NEON_4_H_INCLUDED
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#define ASTC_VECMATHLIB_NEON_4_H_INCLUDED
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#ifndef ASTCENC_SIMD_INLINE
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#error "Include astcenc_vecmathlib.h, do not include directly"
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#endif
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#include <cstdio>
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#include <cstring>
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// ============================================================================
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// vfloat4 data type
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// ============================================================================
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/**
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* @brief Data type for 4-wide floats.
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*/
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struct vfloat4
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{
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/**
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* @brief Construct from zero-initialized value.
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*/
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ASTCENC_SIMD_INLINE vfloat4() = default;
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/**
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* @brief Construct from 4 values loaded from an unaligned address.
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*
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* Consider using loada() which is better with vectors if data is aligned
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* to vector length.
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*/
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ASTCENC_SIMD_INLINE explicit vfloat4(const float *p)
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{
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m = vld1q_f32(p);
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}
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/**
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* @brief Construct from 1 scalar value replicated across all lanes.
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*
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* Consider using zero() for constexpr zeros.
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*/
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ASTCENC_SIMD_INLINE explicit vfloat4(float a)
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{
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m = vdupq_n_f32(a);
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}
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/**
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* @brief Construct from 4 scalar values.
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*
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* The value of @c a is stored to lane 0 (LSB) in the SIMD register.
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*/
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ASTCENC_SIMD_INLINE explicit vfloat4(float a, float b, float c, float d)
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{
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float v[4] { a, b, c, d };
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m = vld1q_f32(v);
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}
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/**
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* @brief Construct from an existing SIMD register.
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*/
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ASTCENC_SIMD_INLINE explicit vfloat4(float32x4_t a)
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{
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m = a;
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}
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/**
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* @brief Get the scalar value of a single lane.
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*/
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template <int l> ASTCENC_SIMD_INLINE float lane() const
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{
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return vgetq_lane_f32(m, l);
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}
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/**
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* @brief Set the scalar value of a single lane.
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*/
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template <int l> ASTCENC_SIMD_INLINE void set_lane(float a)
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{
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m = vsetq_lane_f32(a, m, l);
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}
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/**
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* @brief Factory that returns a vector of zeros.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 zero()
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{
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return vfloat4(0.0f);
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}
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/**
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* @brief Factory that returns a replicated scalar loaded from memory.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 load1(const float* p)
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{
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return vfloat4(vld1q_dup_f32(p));
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}
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/**
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* @brief Factory that returns a vector loaded from 16B aligned memory.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 loada(const float* p)
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{
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return vfloat4(vld1q_f32(p));
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}
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/**
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* @brief Return a swizzled float 2.
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*/
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template <int l0, int l1> ASTCENC_SIMD_INLINE vfloat4 swz() const
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{
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return vfloat4(lane<l0>(), lane<l1>(), 0.0f, 0.0f);
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}
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/**
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* @brief Return a swizzled float 3.
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*/
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template <int l0, int l1, int l2> ASTCENC_SIMD_INLINE vfloat4 swz() const
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{
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return vfloat4(lane<l0>(), lane<l1>(), lane<l2>(), 0.0f);
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}
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/**
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* @brief Return a swizzled float 4.
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*/
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template <int l0, int l1, int l2, int l3> ASTCENC_SIMD_INLINE vfloat4 swz() const
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{
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return vfloat4(lane<l0>(), lane<l1>(), lane<l2>(), lane<l3>());
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}
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/**
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* @brief The vector ...
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*/
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float32x4_t m;
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};
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// ============================================================================
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// vint4 data type
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// ============================================================================
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/**
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* @brief Data type for 4-wide ints.
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*/
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struct vint4
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{
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/**
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* @brief Construct from zero-initialized value.
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*/
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ASTCENC_SIMD_INLINE vint4() = default;
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/**
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* @brief Construct from 4 values loaded from an unaligned address.
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*
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* Consider using loada() which is better with vectors if data is aligned
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* to vector length.
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*/
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ASTCENC_SIMD_INLINE explicit vint4(const int *p)
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{
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m = vld1q_s32(p);
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}
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/**
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* @brief Construct from 4 uint8_t loaded from an unaligned address.
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*/
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ASTCENC_SIMD_INLINE explicit vint4(const uint8_t *p)
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{
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#if ASTCENC_SVE == 0
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// Cast is safe - NEON loads are allowed to be unaligned
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uint32x2_t t8 = vld1_dup_u32(reinterpret_cast<const uint32_t*>(p));
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uint16x4_t t16 = vget_low_u16(vmovl_u8(vreinterpret_u8_u32(t8)));
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m = vreinterpretq_s32_u32(vmovl_u16(t16));
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#else
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svint32_t data = svld1ub_s32(svptrue_pat_b32(SV_VL4), p);
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m = svget_neonq(data);
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#endif
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}
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/**
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* @brief Construct from 1 scalar value replicated across all lanes.
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*
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* Consider using zero() for constexpr zeros.
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*/
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ASTCENC_SIMD_INLINE explicit vint4(int a)
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{
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m = vdupq_n_s32(a);
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}
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/**
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* @brief Construct from 4 scalar values.
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*
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* The value of @c a is stored to lane 0 (LSB) in the SIMD register.
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*/
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ASTCENC_SIMD_INLINE explicit vint4(int a, int b, int c, int d)
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{
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int v[4] { a, b, c, d };
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m = vld1q_s32(v);
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}
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/**
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* @brief Construct from an existing SIMD register.
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*/
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ASTCENC_SIMD_INLINE explicit vint4(int32x4_t a)
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{
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m = a;
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}
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/**
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* @brief Get the scalar from a single lane.
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*/
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template <int l> ASTCENC_SIMD_INLINE int lane() const
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{
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return vgetq_lane_s32(m, l);
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}
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/**
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* @brief Set the scalar value of a single lane.
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*/
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template <int l> ASTCENC_SIMD_INLINE void set_lane(int a)
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{
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m = vsetq_lane_s32(a, m, l);
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}
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/**
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* @brief Factory that returns a vector of zeros.
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*/
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static ASTCENC_SIMD_INLINE vint4 zero()
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{
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return vint4(0);
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}
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/**
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* @brief Factory that returns a replicated scalar loaded from memory.
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*/
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static ASTCENC_SIMD_INLINE vint4 load1(const int* p)
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{
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return vint4(*p);
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}
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/**
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* @brief Factory that returns a vector loaded from unaligned memory.
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*/
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static ASTCENC_SIMD_INLINE vint4 load(const uint8_t* p)
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{
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vint4 data;
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std::memcpy(&data.m, p, 4 * sizeof(int));
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return data;
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}
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/**
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* @brief Factory that returns a vector loaded from 16B aligned memory.
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*/
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static ASTCENC_SIMD_INLINE vint4 loada(const int* p)
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{
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return vint4(p);
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}
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/**
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* @brief Factory that returns a vector containing the lane IDs.
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*/
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static ASTCENC_SIMD_INLINE vint4 lane_id()
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{
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alignas(16) static const int data[4] { 0, 1, 2, 3 };
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return vint4(vld1q_s32(data));
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}
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/**
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* @brief The vector ...
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*/
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int32x4_t m;
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};
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// ============================================================================
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// vmask4 data type
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// ============================================================================
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/**
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* @brief Data type for 4-wide control plane masks.
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*/
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struct vmask4
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{
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/**
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* @brief Construct from an existing SIMD register.
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*/
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ASTCENC_SIMD_INLINE explicit vmask4(uint32x4_t a)
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{
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m = a;
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}
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#if !defined(_MSC_VER)
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/**
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* @brief Construct from an existing SIMD register.
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*/
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ASTCENC_SIMD_INLINE explicit vmask4(int32x4_t a)
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{
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m = vreinterpretq_u32_s32(a);
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}
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#endif
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/**
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* @brief Construct from 1 scalar value.
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*/
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ASTCENC_SIMD_INLINE explicit vmask4(bool a)
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{
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m = vreinterpretq_u32_s32(vdupq_n_s32(a == true ? -1 : 0));
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}
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/**
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* @brief Construct from 4 scalar values.
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*
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* The value of @c a is stored to lane 0 (LSB) in the SIMD register.
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*/
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ASTCENC_SIMD_INLINE explicit vmask4(bool a, bool b, bool c, bool d)
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{
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int v[4] {
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a == true ? -1 : 0,
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b == true ? -1 : 0,
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c == true ? -1 : 0,
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d == true ? -1 : 0
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};
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int32x4_t ms = vld1q_s32(v);
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m = vreinterpretq_u32_s32(ms);
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}
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/**
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* @brief Get the scalar from a single lane.
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*/
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template <int32_t l> ASTCENC_SIMD_INLINE bool lane() const
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{
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return vgetq_lane_u32(m, l) != 0;
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}
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/**
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* @brief The vector ...
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*/
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uint32x4_t m;
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};
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// ============================================================================
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// vmask4 operators and functions
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// ============================================================================
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/**
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* @brief Overload: mask union (or).
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*/
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ASTCENC_SIMD_INLINE vmask4 operator|(vmask4 a, vmask4 b)
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{
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return vmask4(vorrq_u32(a.m, b.m));
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}
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/**
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* @brief Overload: mask intersect (and).
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*/
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ASTCENC_SIMD_INLINE vmask4 operator&(vmask4 a, vmask4 b)
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{
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return vmask4(vandq_u32(a.m, b.m));
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}
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/**
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* @brief Overload: mask difference (xor).
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*/
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ASTCENC_SIMD_INLINE vmask4 operator^(vmask4 a, vmask4 b)
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{
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return vmask4(veorq_u32(a.m, b.m));
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}
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/**
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* @brief Overload: mask invert (not).
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*/
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ASTCENC_SIMD_INLINE vmask4 operator~(vmask4 a)
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{
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return vmask4(vmvnq_u32(a.m));
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}
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/**
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* @brief Return a 4-bit mask code indicating mask status.
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*
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* bit0 = lane 0
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*/
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ASTCENC_SIMD_INLINE unsigned int mask(vmask4 a)
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{
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static const int shifta[4] { 0, 1, 2, 3 };
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static const int32x4_t shift = vld1q_s32(shifta);
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uint32x4_t tmp = vshrq_n_u32(a.m, 31);
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return vaddvq_u32(vshlq_u32(tmp, shift));
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}
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/**
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* @brief True if any lanes are enabled, false otherwise.
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*/
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ASTCENC_SIMD_INLINE bool any(vmask4 a)
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{
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return vmaxvq_u32(a.m) != 0;
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}
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/**
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* @brief True if all lanes are enabled, false otherwise.
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*/
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ASTCENC_SIMD_INLINE bool all(vmask4 a)
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{
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return vminvq_u32(a.m) != 0;
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}
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// ============================================================================
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// vint4 operators and functions
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// ============================================================================
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/**
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* @brief Overload: vector by vector addition.
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*/
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ASTCENC_SIMD_INLINE vint4 operator+(vint4 a, vint4 b)
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{
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return vint4(vaddq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector by vector subtraction.
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*/
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ASTCENC_SIMD_INLINE vint4 operator-(vint4 a, vint4 b)
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{
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return vint4(vsubq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector by vector multiplication.
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*/
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ASTCENC_SIMD_INLINE vint4 operator*(vint4 a, vint4 b)
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{
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return vint4(vmulq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector bit invert.
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*/
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ASTCENC_SIMD_INLINE vint4 operator~(vint4 a)
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{
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return vint4(vmvnq_s32(a.m));
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}
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/**
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* @brief Overload: vector by vector bitwise or.
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*/
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ASTCENC_SIMD_INLINE vint4 operator|(vint4 a, vint4 b)
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{
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return vint4(vorrq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector by vector bitwise and.
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*/
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ASTCENC_SIMD_INLINE vint4 operator&(vint4 a, vint4 b)
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{
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return vint4(vandq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector by vector bitwise xor.
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*/
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ASTCENC_SIMD_INLINE vint4 operator^(vint4 a, vint4 b)
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{
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return vint4(veorq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector by vector equality.
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*/
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ASTCENC_SIMD_INLINE vmask4 operator==(vint4 a, vint4 b)
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{
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return vmask4(vceqq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector by vector inequality.
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*/
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ASTCENC_SIMD_INLINE vmask4 operator!=(vint4 a, vint4 b)
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{
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return ~vmask4(vceqq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector by vector less than.
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*/
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ASTCENC_SIMD_INLINE vmask4 operator<(vint4 a, vint4 b)
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{
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return vmask4(vcltq_s32(a.m, b.m));
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}
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/**
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* @brief Overload: vector by vector greater than.
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*/
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ASTCENC_SIMD_INLINE vmask4 operator>(vint4 a, vint4 b)
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{
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return vmask4(vcgtq_s32(a.m, b.m));
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}
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/**
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* @brief Logical shift left.
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*/
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template <int s> ASTCENC_SIMD_INLINE vint4 lsl(vint4 a)
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{
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return vint4(vshlq_s32(a.m, vdupq_n_s32(s)));
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}
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/**
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* @brief Logical shift right.
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*/
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template <int s> ASTCENC_SIMD_INLINE vint4 lsr(vint4 a)
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{
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uint32x4_t ua = vreinterpretq_u32_s32(a.m);
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ua = vshlq_u32(ua, vdupq_n_s32(-s));
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return vint4(vreinterpretq_s32_u32(ua));
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}
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/**
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* @brief Arithmetic shift right.
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*/
|
|
template <int s> ASTCENC_SIMD_INLINE vint4 asr(vint4 a)
|
|
{
|
|
return vint4(vshlq_s32(a.m, vdupq_n_s32(-s)));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the min vector of two vectors.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 min(vint4 a, vint4 b)
|
|
{
|
|
return vint4(vminq_s32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the max vector of two vectors.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 max(vint4 a, vint4 b)
|
|
{
|
|
return vint4(vmaxq_s32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the horizontal minimum of a vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 hmin(vint4 a)
|
|
{
|
|
return vint4(vminvq_s32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the horizontal maximum of a vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 hmax(vint4 a)
|
|
{
|
|
return vint4(vmaxvq_s32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Store a vector to a 16B aligned memory address.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void storea(vint4 a, int* p)
|
|
{
|
|
vst1q_s32(p, a.m);
|
|
}
|
|
|
|
/**
|
|
* @brief Store a vector to an unaligned memory address.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void store(vint4 a, int* p)
|
|
{
|
|
vst1q_s32(p, a.m);
|
|
}
|
|
|
|
/**
|
|
* @brief Store a vector to an unaligned memory address.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void store(vint4 a, uint8_t* p)
|
|
{
|
|
std::memcpy(p, &a.m, sizeof(int) * 4);
|
|
}
|
|
|
|
/**
|
|
* @brief Store lowest N (vector width) bytes into an unaligned address.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void store_nbytes(vint4 a, uint8_t* p)
|
|
{
|
|
vst1q_lane_s32(reinterpret_cast<int32_t*>(p), a.m, 0);
|
|
}
|
|
|
|
/**
|
|
* @brief Pack and store low 8 bits of each vector lane.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void pack_and_store_low_bytes(vint4 a, uint8_t* data)
|
|
{
|
|
alignas(16) uint8_t shuf[16] {
|
|
0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
|
};
|
|
uint8x16_t idx = vld1q_u8(shuf);
|
|
int8x16_t av = vreinterpretq_s8_s32(a.m);
|
|
a = vint4(vreinterpretq_s32_s8(vqtbl1q_s8(av, idx)));
|
|
store_nbytes(a, data);
|
|
}
|
|
|
|
/**
|
|
* @brief Return lanes from @c b if @c cond is set, else @c a.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 select(vint4 a, vint4 b, vmask4 cond)
|
|
{
|
|
return vint4(vbslq_s32(cond.m, b.m, a.m));
|
|
}
|
|
|
|
// ============================================================================
|
|
// vfloat4 operators and functions
|
|
// ============================================================================
|
|
|
|
/**
|
|
* @brief Overload: vector by vector addition.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 operator+(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vfloat4(vaddq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector subtraction.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 operator-(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vfloat4(vsubq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector multiplication.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 operator*(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vfloat4(vmulq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector division.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 operator/(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vfloat4(vdivq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector equality.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vmask4 operator==(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vmask4(vceqq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector inequality.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vmask4 operator!=(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vmask4(vmvnq_u32(vceqq_f32(a.m, b.m)));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector less than.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vmask4 operator<(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vmask4(vcltq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector greater than.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vmask4 operator>(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vmask4(vcgtq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector less than or equal.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vmask4 operator<=(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vmask4(vcleq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Overload: vector by vector greater than or equal.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vmask4 operator>=(vfloat4 a, vfloat4 b)
|
|
{
|
|
return vmask4(vcgeq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the min vector of two vectors.
|
|
*
|
|
* If either lane value is NaN, @c b will be returned for that lane.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 min(vfloat4 a, vfloat4 b)
|
|
{
|
|
// Do not reorder - second operand will return if either is NaN
|
|
return vfloat4(vminnmq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the max vector of two vectors.
|
|
*
|
|
* If either lane value is NaN, @c b will be returned for that lane.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 max(vfloat4 a, vfloat4 b)
|
|
{
|
|
// Do not reorder - second operand will return if either is NaN
|
|
return vfloat4(vmaxnmq_f32(a.m, b.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the absolute value of the float vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 abs(vfloat4 a)
|
|
{
|
|
float32x4_t zero = vdupq_n_f32(0.0f);
|
|
float32x4_t inv = vsubq_f32(zero, a.m);
|
|
return vfloat4(vmaxq_f32(a.m, inv));
|
|
}
|
|
|
|
/**
|
|
* @brief Return a float rounded to the nearest integer value.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 round(vfloat4 a)
|
|
{
|
|
return vfloat4(vrndnq_f32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the horizontal minimum of a vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 hmin(vfloat4 a)
|
|
{
|
|
return vfloat4(vminvq_f32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the horizontal maximum of a vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 hmax(vfloat4 a)
|
|
{
|
|
return vfloat4(vmaxvq_f32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the horizontal sum of a vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE float hadd_s(vfloat4 a)
|
|
{
|
|
// Perform halving add to ensure invariance; we cannot use vaddqv as this
|
|
// does (0 + 1 + 2 + 3) which is not invariant with x86 (0 + 2) + (1 + 3).
|
|
float32x2_t t = vadd_f32(vget_high_f32(a.m), vget_low_f32(a.m));
|
|
return vget_lane_f32(vpadd_f32(t, t), 0);
|
|
}
|
|
|
|
/**
|
|
* @brief Return the sqrt of the lanes in the vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 sqrt(vfloat4 a)
|
|
{
|
|
return vfloat4(vsqrtq_f32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return lanes from @c b if @c cond is set, else @c a.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 select(vfloat4 a, vfloat4 b, vmask4 cond)
|
|
{
|
|
return vfloat4(vbslq_f32(cond.m, b.m, a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Load a vector of gathered results from an array;
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 gatherf(const float* base, vint4 indices)
|
|
{
|
|
#if ASTCENC_SVE == 0
|
|
alignas(16) int idx[4];
|
|
storea(indices, idx);
|
|
alignas(16) float vals[4];
|
|
vals[0] = base[idx[0]];
|
|
vals[1] = base[idx[1]];
|
|
vals[2] = base[idx[2]];
|
|
vals[3] = base[idx[3]];
|
|
return vfloat4(vals);
|
|
#else
|
|
svint32_t offsets = svset_neonq_s32(svundef_s32(), indices.m);
|
|
svfloat32_t data = svld1_gather_s32index_f32(svptrue_pat_b32(SV_VL4), base, offsets);
|
|
return vfloat4(svget_neonq_f32(data));
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* @brief Load a vector of gathered results from an array using byte indices from memory
|
|
*/
|
|
template<>
|
|
ASTCENC_SIMD_INLINE vfloat4 gatherf_byte_inds<vfloat4>(const float* base, const uint8_t* indices)
|
|
{
|
|
#if ASTCENC_SVE == 0
|
|
alignas(16) float vals[4];
|
|
vals[0] = base[indices[0]];
|
|
vals[1] = base[indices[1]];
|
|
vals[2] = base[indices[2]];
|
|
vals[3] = base[indices[3]];
|
|
return vfloat4(vals);
|
|
#else
|
|
svint32_t offsets = svld1ub_s32(svptrue_pat_b32(SV_VL4), indices);
|
|
svfloat32_t data = svld1_gather_s32index_f32(svptrue_pat_b32(SV_VL4), base, offsets);
|
|
return vfloat4(svget_neonq_f32(data));
|
|
#endif
|
|
}
|
|
/**
|
|
* @brief Store a vector to an unaligned memory address.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void store(vfloat4 a, float* p)
|
|
{
|
|
vst1q_f32(p, a.m);
|
|
}
|
|
|
|
/**
|
|
* @brief Store a vector to a 16B aligned memory address.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void storea(vfloat4 a, float* p)
|
|
{
|
|
vst1q_f32(p, a.m);
|
|
}
|
|
|
|
/**
|
|
* @brief Return a integer value for a float vector, using truncation.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 float_to_int(vfloat4 a)
|
|
{
|
|
return vint4(vcvtq_s32_f32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return a integer value for a float vector, using round-to-nearest.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 float_to_int_rtn(vfloat4 a)
|
|
{
|
|
a = a + vfloat4(0.5f);
|
|
return vint4(vcvtq_s32_f32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return a float value for an integer vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 int_to_float(vint4 a)
|
|
{
|
|
return vfloat4(vcvtq_f32_s32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return a float16 value for a float vector, using round-to-nearest.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 float_to_float16(vfloat4 a)
|
|
{
|
|
// Generate float16 value
|
|
float16x4_t f16 = vcvt_f16_f32(a.m);
|
|
|
|
// Convert each 16-bit float pattern to a 32-bit pattern
|
|
uint16x4_t u16 = vreinterpret_u16_f16(f16);
|
|
uint32x4_t u32 = vmovl_u16(u16);
|
|
return vint4(vreinterpretq_s32_u32(u32));
|
|
}
|
|
|
|
/**
|
|
* @brief Return a float16 value for a float scalar, using round-to-nearest.
|
|
*/
|
|
static inline uint16_t float_to_float16(float a)
|
|
{
|
|
vfloat4 av(a);
|
|
return static_cast<uint16_t>(float_to_float16(av).lane<0>());
|
|
}
|
|
|
|
/**
|
|
* @brief Return a float value for a float16 vector.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 float16_to_float(vint4 a)
|
|
{
|
|
// Convert each 32-bit float pattern to a 16-bit pattern
|
|
uint32x4_t u32 = vreinterpretq_u32_s32(a.m);
|
|
uint16x4_t u16 = vmovn_u32(u32);
|
|
float16x4_t f16 = vreinterpret_f16_u16(u16);
|
|
|
|
// Generate float16 value
|
|
return vfloat4(vcvt_f32_f16(f16));
|
|
}
|
|
|
|
/**
|
|
* @brief Return a float value for a float16 scalar.
|
|
*/
|
|
ASTCENC_SIMD_INLINE float float16_to_float(uint16_t a)
|
|
{
|
|
vint4 av(a);
|
|
return float16_to_float(av).lane<0>();
|
|
}
|
|
|
|
/**
|
|
* @brief Return a float value as an integer bit pattern (i.e. no conversion).
|
|
*
|
|
* It is a common trick to convert floats into integer bit patterns, perform
|
|
* some bit hackery based on knowledge they are IEEE 754 layout, and then
|
|
* convert them back again. This is the first half of that flip.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 float_as_int(vfloat4 a)
|
|
{
|
|
return vint4(vreinterpretq_s32_f32(a.m));
|
|
}
|
|
|
|
/**
|
|
* @brief Return a integer value as a float bit pattern (i.e. no conversion).
|
|
*
|
|
* It is a common trick to convert floats into integer bit patterns, perform
|
|
* some bit hackery based on knowledge they are IEEE 754 layout, and then
|
|
* convert them back again. This is the second half of that flip.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vfloat4 int_as_float(vint4 v)
|
|
{
|
|
return vfloat4(vreinterpretq_f32_s32(v.m));
|
|
}
|
|
|
|
/*
|
|
* Table structure for a 16x 8-bit entry table.
|
|
*/
|
|
struct vtable4_16x8 {
|
|
uint8x16_t t0;
|
|
};
|
|
|
|
/*
|
|
* Table structure for a 32x 8-bit entry table.
|
|
*/
|
|
struct vtable4_32x8 {
|
|
uint8x16x2_t t01;
|
|
};
|
|
|
|
/*
|
|
* Table structure for a 64x 8-bit entry table.
|
|
*/
|
|
struct vtable4_64x8 {
|
|
uint8x16x4_t t0123;
|
|
};
|
|
|
|
/**
|
|
* @brief Prepare a vtable lookup table for 16x 8-bit entry table.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void vtable_prepare(
|
|
vtable4_16x8& table,
|
|
const uint8_t* data
|
|
) {
|
|
table.t0 = vld1q_u8(data);
|
|
}
|
|
|
|
/**
|
|
* @brief Prepare a vtable lookup table for 32x 8-bit entry table.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void vtable_prepare(
|
|
vtable4_32x8& table,
|
|
const uint8_t* data
|
|
) {
|
|
table.t01 = uint8x16x2_t {
|
|
vld1q_u8(data),
|
|
vld1q_u8(data + 16)
|
|
};
|
|
}
|
|
|
|
/**
|
|
* @brief Prepare a vtable lookup table 64x 8-bit entry table.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void vtable_prepare(
|
|
vtable4_64x8& table,
|
|
const uint8_t* data
|
|
) {
|
|
table.t0123 = uint8x16x4_t {
|
|
vld1q_u8(data),
|
|
vld1q_u8(data + 16),
|
|
vld1q_u8(data + 32),
|
|
vld1q_u8(data + 48)
|
|
};
|
|
}
|
|
|
|
/**
|
|
* @brief Perform a vtable lookup in a 16x 8-bit table with 32-bit indices.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 vtable_lookup_32bit(
|
|
const vtable4_16x8& tbl,
|
|
vint4 idx
|
|
) {
|
|
// Set index byte above max index for unused bytes so table lookup returns zero
|
|
int32x4_t idx_masked = vorrq_s32(idx.m, vdupq_n_s32(0xFFFFFF00));
|
|
uint8x16_t idx_bytes = vreinterpretq_u8_s32(idx_masked);
|
|
|
|
return vint4(vreinterpretq_s32_u8(vqtbl1q_u8(tbl.t0, idx_bytes)));
|
|
}
|
|
|
|
/**
|
|
* @brief Perform a vtable lookup in a 32x 8-bit table with 32-bit indices.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 vtable_lookup_32bit(
|
|
const vtable4_32x8& tbl,
|
|
vint4 idx
|
|
) {
|
|
// Set index byte above max index for unused bytes so table lookup returns zero
|
|
int32x4_t idx_masked = vorrq_s32(idx.m, vdupq_n_s32(0xFFFFFF00));
|
|
uint8x16_t idx_bytes = vreinterpretq_u8_s32(idx_masked);
|
|
|
|
return vint4(vreinterpretq_s32_u8(vqtbl2q_u8(tbl.t01, idx_bytes)));
|
|
}
|
|
|
|
/**
|
|
* @brief Perform a vtable lookup in a 64x 8-bit table with 32-bit indices.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 vtable_lookup_32bit(
|
|
const vtable4_64x8& tbl,
|
|
vint4 idx
|
|
) {
|
|
// Set index byte above max index for unused bytes so table lookup returns zero
|
|
int32x4_t idx_masked = vorrq_s32(idx.m, vdupq_n_s32(0xFFFFFF00));
|
|
uint8x16_t idx_bytes = vreinterpretq_u8_s32(idx_masked);
|
|
|
|
return vint4(vreinterpretq_s32_u8(vqtbl4q_u8(tbl.t0123, idx_bytes)));
|
|
}
|
|
|
|
/**
|
|
* @brief Return a vector of interleaved RGBA data.
|
|
*
|
|
* Input vectors have the value stored in the bottom 8 bits of each lane,
|
|
* with high bits set to zero.
|
|
*
|
|
* Output vector stores a single RGBA texel packed in each lane.
|
|
*/
|
|
ASTCENC_SIMD_INLINE vint4 interleave_rgba8(vint4 r, vint4 g, vint4 b, vint4 a)
|
|
{
|
|
return r + lsl<8>(g) + lsl<16>(b) + lsl<24>(a);
|
|
}
|
|
|
|
/**
|
|
* @brief Store a single vector lane to an unaligned address.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void store_lane(uint8_t* base, int data)
|
|
{
|
|
std::memcpy(base, &data, sizeof(int));
|
|
}
|
|
|
|
/**
|
|
* @brief Store a vector, skipping masked lanes.
|
|
*
|
|
* All masked lanes must be at the end of vector, after all non-masked lanes.
|
|
*/
|
|
ASTCENC_SIMD_INLINE void store_lanes_masked(uint8_t* base, vint4 data, vmask4 mask)
|
|
{
|
|
if (mask.lane<3>())
|
|
{
|
|
store(data, base);
|
|
}
|
|
else if (mask.lane<2>() != 0.0f)
|
|
{
|
|
store_lane(base + 0, data.lane<0>());
|
|
store_lane(base + 4, data.lane<1>());
|
|
store_lane(base + 8, data.lane<2>());
|
|
}
|
|
else if (mask.lane<1>() != 0.0f)
|
|
{
|
|
store_lane(base + 0, data.lane<0>());
|
|
store_lane(base + 4, data.lane<1>());
|
|
}
|
|
else if (mask.lane<0>() != 0.0f)
|
|
{
|
|
store_lane(base + 0, data.lane<0>());
|
|
}
|
|
}
|
|
|
|
#define ASTCENC_USE_NATIVE_POPCOUNT 1
|
|
|
|
/**
|
|
* @brief Population bit count.
|
|
*
|
|
* @param v The value to population count.
|
|
*
|
|
* @return The number of 1 bits.
|
|
*/
|
|
ASTCENC_SIMD_INLINE int popcount(uint64_t v)
|
|
{
|
|
return static_cast<int>(vaddlv_u8(vcnt_u8(vcreate_u8(v))));
|
|
}
|
|
|
|
#endif // #ifndef ASTC_VECMATHLIB_NEON_4_H_INCLUDED
|