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This is mostly a maintenance update that brings the compressor inline with the recently published Khronos Data Format Specification 1.4 release which clarified some ambiguity in the specification. This update also gives minor codec optimizations, bug fixes, and image quality improvements. The biggest improvement for Godot is that builds using MSVC cl.exe will now correctly default to the SSE2-optimized backend rather than the reference C backend. This makes compression more than 3 times faster. Builds using other compilers (GCC, LLVM/Clang) were not impacted by the underlying issue, and see no performance uplift.
609 lines
16 KiB
C++
609 lines
16 KiB
C++
// SPDX-License-Identifier: Apache-2.0
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// ----------------------------------------------------------------------------
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// Copyright 2019-2025 Arm Limited
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// Copyright 2008 Jose Fonseca
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//
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// Licensed under the Apache License, Version 2.0 (the "License"); you may not
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// use this file except in compliance with the License. You may obtain a copy
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// of the License at:
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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// ----------------------------------------------------------------------------
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/*
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* This module implements vector support for floats, ints, and vector lane
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* control masks. It provides access to both explicit vector width types, and
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* flexible N-wide types where N can be determined at compile time.
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*
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* The design of this module encourages use of vector length agnostic code, via
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* the vint, vfloat, and vmask types. These will take on the widest SIMD vector
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* with that is available at compile time. The current vector width is
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* accessible for e.g. loop strides via the ASTCENC_SIMD_WIDTH constant.
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*
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* Explicit scalar types are accessible via the vint1, vfloat1, vmask1 types.
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* These are provided primarily for prototyping and algorithm debug of VLA
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* implementations.
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*
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* Explicit 4-wide types are accessible via the vint4, vfloat4, and vmask4
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* types. These are provided for use by VLA code, but are also expected to be
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* used as a fixed-width type and will supported a reference C++ fallback for
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* use on platforms without SIMD intrinsics.
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*
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* Explicit 8-wide types are accessible via the vint8, vfloat8, and vmask8
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* types. These are provide for use by VLA code, and are not expected to be
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* used as a fixed-width type in normal code. No reference C implementation is
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* provided on platforms without underlying SIMD intrinsics.
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*
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* With the current implementation ISA support is provided for:
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*
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* * 1-wide for scalar reference
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* * 4-wide for Armv8-A NEON
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* * 4-wide for x86-64 SSE2
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* * 4-wide for x86-64 SSE4.1
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* * 8-wide for Armv8-A SVE
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* * 8-wide for x86-64 AVX2
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*/
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#ifndef ASTC_VECMATHLIB_H_INCLUDED
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#define ASTC_VECMATHLIB_H_INCLUDED
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#if ASTCENC_SSE != 0 || ASTCENC_AVX != 0
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#include <immintrin.h>
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#endif
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#if ASTCENC_SVE != 0
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#include <arm_sve.h>
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#include <arm_neon_sve_bridge.h>
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#endif
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#if ASTCENC_NEON != 0
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#include <arm_neon.h>
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#endif
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#if !defined(__clang__) && defined(_MSC_VER)
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#define ASTCENC_SIMD_INLINE __forceinline
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#define ASTCENC_NO_INLINE
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#elif defined(__GNUC__) && !defined(__clang__)
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#define ASTCENC_SIMD_INLINE __attribute__((always_inline)) inline
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#define ASTCENC_NO_INLINE __attribute__ ((noinline))
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#else
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#define ASTCENC_SIMD_INLINE __attribute__((always_inline, nodebug)) inline
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#define ASTCENC_NO_INLINE __attribute__ ((noinline))
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#endif
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template<typename T> T gatherf_byte_inds(const float* base, const uint8_t* indices);
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#if ASTCENC_AVX >= 2
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// If we have AVX2 expose 8-wide VLA.
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#include "astcenc_vecmathlib_sse_4.h"
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#include "astcenc_vecmathlib_common_4.h"
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#include "astcenc_vecmathlib_avx2_8.h"
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#define ASTCENC_SIMD_WIDTH 8
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using vfloat = vfloat8;
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#if defined(ASTCENC_NO_INVARIANCE)
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using vfloatacc = vfloat8;
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#else
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using vfloatacc = vfloat4;
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#endif
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using vint = vint8;
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using vmask = vmask8;
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using vtable_16x8 = vtable8_16x8;
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using vtable_32x8 = vtable8_32x8;
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using vtable_64x8 = vtable8_64x8;
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constexpr auto loada = vfloat8::loada;
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constexpr auto load1 = vfloat8::load1;
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constexpr auto vint_from_size = vint8_from_size;
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#elif ASTCENC_SSE >= 20
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// If we have SSE expose 4-wide VLA, and 4-wide fixed width.
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#include "astcenc_vecmathlib_sse_4.h"
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#include "astcenc_vecmathlib_common_4.h"
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#define ASTCENC_SIMD_WIDTH 4
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using vfloat = vfloat4;
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using vfloatacc = vfloat4;
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using vint = vint4;
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using vmask = vmask4;
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using vtable_16x8 = vtable4_16x8;
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using vtable_32x8 = vtable4_32x8;
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using vtable_64x8 = vtable4_64x8;
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constexpr auto loada = vfloat4::loada;
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constexpr auto load1 = vfloat4::load1;
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constexpr auto vint_from_size = vint4_from_size;
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#elif ASTCENC_SVE == 8
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// Check the compiler is configured with fixed-length 256-bit SVE.
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#if !defined(__ARM_FEATURE_SVE_BITS) || (__ARM_FEATURE_SVE_BITS != 256)
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#error "__ARM_FEATURE_SVE_BITS is not set to 256 bits"
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#endif
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// If we have SVE configured as 8-wide, expose 8-wide VLA.
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#include "astcenc_vecmathlib_neon_4.h"
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#include "astcenc_vecmathlib_common_4.h"
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#include "astcenc_vecmathlib_sve_8.h"
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#define ASTCENC_SIMD_WIDTH 8
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using vfloat = vfloat8;
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#if defined(ASTCENC_NO_INVARIANCE)
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using vfloatacc = vfloat8;
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#else
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using vfloatacc = vfloat4;
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#endif
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using vint = vint8;
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using vmask = vmask8;
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using vtable_16x8 = vtable8_16x8;
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using vtable_32x8 = vtable8_32x8;
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using vtable_64x8 = vtable8_64x8;
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constexpr auto loada = vfloat8::loada;
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constexpr auto load1 = vfloat8::load1;
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constexpr auto vint_from_size = vint8_from_size;
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#elif ASTCENC_NEON > 0
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// If we have NEON expose 4-wide VLA.
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#include "astcenc_vecmathlib_neon_4.h"
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#include "astcenc_vecmathlib_common_4.h"
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#define ASTCENC_SIMD_WIDTH 4
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using vfloat = vfloat4;
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using vfloatacc = vfloat4;
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using vint = vint4;
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using vmask = vmask4;
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using vtable_16x8 = vtable4_16x8;
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using vtable_32x8 = vtable4_32x8;
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using vtable_64x8 = vtable4_64x8;
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constexpr auto loada = vfloat4::loada;
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constexpr auto load1 = vfloat4::load1;
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constexpr auto vint_from_size = vint4_from_size;
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#else
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// If we have nothing expose 4-wide VLA, and 4-wide fixed width.
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// Note: We no longer expose the 1-wide scalar fallback because it is not
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// invariant with the 4-wide path due to algorithms that use horizontal
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// operations that accumulate a local vector sum before accumulating into
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// a running sum.
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//
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// For 4 items adding into an accumulator using 1-wide vectors the sum is:
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//
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// result = ((((sum + l0) + l1) + l2) + l3)
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//
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// ... whereas the accumulator for a 4-wide vector sum is:
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//
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// result = sum + ((l0 + l2) + (l1 + l3))
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//
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// In "normal maths" this is the same, but the floating point reassociation
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// differences mean that these will not produce the same result.
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#include "astcenc_vecmathlib_none_4.h"
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#include "astcenc_vecmathlib_common_4.h"
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#define ASTCENC_SIMD_WIDTH 4
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using vfloat = vfloat4;
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using vfloatacc = vfloat4;
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using vint = vint4;
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using vmask = vmask4;
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using vtable_16x8 = vtable4_16x8;
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using vtable_32x8 = vtable4_32x8;
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using vtable_64x8 = vtable4_64x8;
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constexpr auto loada = vfloat4::loada;
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constexpr auto load1 = vfloat4::load1;
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constexpr auto vint_from_size = vint4_from_size;
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#endif
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/**
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* @brief Round a count down to the largest multiple of the SIMD width.
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*
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* Assumption that the vector width is a power of two ...
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*
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* @param count The unrounded value.
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*
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* @return The rounded value.
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*/
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ASTCENC_SIMD_INLINE size_t round_down_to_simd_multiple_vla(size_t count)
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{
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return count & static_cast<size_t>(~(ASTCENC_SIMD_WIDTH - 1));
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}
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/**
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* @brief Round a count up to the largest multiple of the SIMD width.
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*
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* Assumption that the vector width is a power of two ...
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*
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* @param count The unrounded value.
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*
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* @return The rounded value.
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*/
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ASTCENC_SIMD_INLINE size_t round_up_to_simd_multiple_vla(size_t count)
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{
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size_t multiples = (count + ASTCENC_SIMD_WIDTH - 1) / ASTCENC_SIMD_WIDTH;
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return multiples * ASTCENC_SIMD_WIDTH;
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}
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/**
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* @brief Return @c a with lanes negated if the @c b lane is negative.
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*/
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ASTCENC_SIMD_INLINE vfloat change_sign(vfloat a, vfloat b)
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{
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vint ia = float_as_int(a);
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vint ib = float_as_int(b);
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vint sign_mask(static_cast<int>(0x80000000));
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vint r = ia ^ (ib & sign_mask);
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return int_as_float(r);
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}
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/**
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* @brief Return fast, but approximate, vector atan(x).
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*
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* Max error of this implementation is 0.004883.
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*/
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ASTCENC_SIMD_INLINE vfloat atan(vfloat x)
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{
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vmask c = abs(x) > vfloat(1.0f);
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vfloat z = change_sign(vfloat(astc::PI_OVER_TWO), x);
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vfloat y = select(x, vfloat(1.0f) / x, c);
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y = y / (y * y * vfloat(0.28f) + vfloat(1.0f));
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return select(y, z - y, c);
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}
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/**
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* @brief Return fast, but approximate, vector atan2(x, y).
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*/
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ASTCENC_SIMD_INLINE vfloat atan2(vfloat y, vfloat x)
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{
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vfloat z = atan(abs(y / x));
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vmask xmask = x < vfloat::zero();
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return change_sign(select(z, vfloat(astc::PI) - z, xmask), y);
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}
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/*
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* @brief Factory that returns a unit length 4 component vfloat4.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 unit4()
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{
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return vfloat4(0.5f);
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}
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/**
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* @brief Factory that returns a unit length 3 component vfloat4.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 unit3()
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{
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float val = 0.577350258827209473f;
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return vfloat4(val, val, val, 0.0f);
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}
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/**
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* @brief Factory that returns a unit length 2 component vfloat4.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 unit2()
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{
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float val = 0.707106769084930420f;
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return vfloat4(val, val, 0.0f, 0.0f);
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}
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/**
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* @brief Factory that returns a 3 component vfloat4.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 vfloat3(float a, float b, float c)
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{
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return vfloat4(a, b, c, 0.0f);
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}
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/**
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* @brief Factory that returns a 2 component vfloat4.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 vfloat2(float a, float b)
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{
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return vfloat4(a, b, 0.0f, 0.0f);
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}
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/**
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* @brief Normalize a non-zero length vector to unit length.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 normalize(vfloat4 a)
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{
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vfloat4 length = dot(a, a);
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return a / sqrt(length);
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}
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/**
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* @brief Normalize a vector, returning @c safe if len is zero.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 normalize_safe(vfloat4 a, vfloat4 safe)
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{
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vfloat4 length = dot(a, a);
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if (length.lane<0>() != 0.0f)
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{
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return a / sqrt(length);
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}
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return safe;
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}
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#define POLY0(x, c0) ( c0)
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#define POLY1(x, c0, c1) ((POLY0(x, c1) * x) + c0)
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#define POLY2(x, c0, c1, c2) ((POLY1(x, c1, c2) * x) + c0)
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#define POLY3(x, c0, c1, c2, c3) ((POLY2(x, c1, c2, c3) * x) + c0)
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#define POLY4(x, c0, c1, c2, c3, c4) ((POLY3(x, c1, c2, c3, c4) * x) + c0)
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#define POLY5(x, c0, c1, c2, c3, c4, c5) ((POLY4(x, c1, c2, c3, c4, c5) * x) + c0)
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/**
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* @brief Compute an approximate exp2(x) for each lane in the vector.
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*
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* Based on 5th degree minimax polynomials, ported from this blog
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* https://jrfonseca.blogspot.com/2008/09/fast-sse2-pow-tables-or-polynomials.html
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*/
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static ASTCENC_SIMD_INLINE vfloat4 exp2(vfloat4 x)
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{
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x = clamp(-126.99999f, 129.0f, x);
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vint4 ipart = float_to_int(x - 0.5f);
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vfloat4 fpart = x - int_to_float(ipart);
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// Integer contrib, using 1 << ipart
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vfloat4 iexp = int_as_float(lsl<23>(ipart + 127));
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// Fractional contrib, using polynomial fit of 2^x in range [-0.5, 0.5)
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vfloat4 fexp = POLY5(fpart,
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9.9999994e-1f,
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6.9315308e-1f,
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2.4015361e-1f,
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5.5826318e-2f,
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8.9893397e-3f,
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1.8775767e-3f);
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return iexp * fexp;
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}
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/**
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* @brief Compute an approximate log2(x) for each lane in the vector.
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*
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* Based on 5th degree minimax polynomials, ported from this blog
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* https://jrfonseca.blogspot.com/2008/09/fast-sse2-pow-tables-or-polynomials.html
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*/
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static ASTCENC_SIMD_INLINE vfloat4 log2(vfloat4 x)
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{
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vint4 exp(0x7F800000);
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vint4 mant(0x007FFFFF);
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vint4 one(0x3F800000);
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vint4 i = float_as_int(x);
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vfloat4 e = int_to_float(lsr<23>(i & exp) - 127);
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vfloat4 m = int_as_float((i & mant) | one);
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// Polynomial fit of log2(x)/(x - 1), for x in range [1, 2)
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vfloat4 p = POLY4(m,
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2.8882704548164776201f,
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-2.52074962577807006663f,
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1.48116647521213171641f,
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-0.465725644288844778798f,
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0.0596515482674574969533f);
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// Increases the polynomial degree, but ensures that log2(1) == 0
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p = p * (m - 1.0f);
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return p + e;
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}
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/**
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* @brief Compute an approximate pow(x, y) for each lane in the vector.
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*
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* Power function based on the exp2(log2(x) * y) transform.
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*/
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static ASTCENC_SIMD_INLINE vfloat4 pow(vfloat4 x, vfloat4 y)
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{
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vmask4 zero_mask = y == vfloat4(0.0f);
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vfloat4 estimate = exp2(log2(x) * y);
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// Guarantee that y == 0 returns exactly 1.0f
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return select(estimate, vfloat4(1.0f), zero_mask);
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}
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/**
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* @brief Count the leading zeros for each lane in @c a.
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*
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* Valid for all data values of @c a; will return a per-lane value [0, 32].
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*/
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static ASTCENC_SIMD_INLINE vint4 clz(vint4 a)
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{
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// This function is a horrible abuse of floating point exponents to convert
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// the original integer value into a 2^N encoding we can recover easily.
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// Convert to float without risk of rounding up by keeping only top 8 bits.
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// This trick is is guaranteed to keep top 8 bits and clear the 9th.
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a = (~lsr<8>(a)) & a;
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a = float_as_int(int_to_float(a));
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// Extract and unbias exponent
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a = vint4(127 + 31) - lsr<23>(a);
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// Clamp result to a valid 32-bit range
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return clamp(0, 32, a);
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}
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/**
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* @brief Return lanewise 2^a for each lane in @c a.
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*
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* Use of signed int means that this is only valid for values in range [0, 31].
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*/
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static ASTCENC_SIMD_INLINE vint4 two_to_the_n(vint4 a)
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{
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// 2^30 is the largest signed number than can be represented
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assert(all(a < vint4(31)));
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// This function is a horrible abuse of floating point to use the exponent
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// and float conversion to generate a 2^N multiple.
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|
|
|
// Bias the exponent
|
|
vint4 exp = a + 127;
|
|
exp = lsl<23>(exp);
|
|
|
|
// Reinterpret the bits as a float, and then convert to an int
|
|
vfloat4 f = int_as_float(exp);
|
|
return float_to_int(f);
|
|
}
|
|
|
|
/**
|
|
* @brief Convert unorm16 [0, 65535] to float16 in range [0, 1].
|
|
*/
|
|
static ASTCENC_SIMD_INLINE vint4 unorm16_to_sf16(vint4 p)
|
|
{
|
|
vint4 fp16_one = vint4(0x3C00);
|
|
vint4 fp16_small = lsl<8>(p);
|
|
|
|
vmask4 is_one = p == vint4(0xFFFF);
|
|
vmask4 is_small = p < vint4(4);
|
|
|
|
// Manually inline clz() on Visual Studio to avoid release build codegen bug
|
|
// see https://github.com/ARM-software/astc-encoder/issues/259
|
|
#if !defined(__clang__) && defined(_MSC_VER)
|
|
vint4 a = (~lsr<8>(p)) & p;
|
|
a = float_as_int(int_to_float(a));
|
|
a = vint4(127 + 31) - lsr<23>(a);
|
|
vint4 lz = clamp(0, 32, a) - 16;
|
|
#else
|
|
vint4 lz = clz(p) - 16;
|
|
#endif
|
|
|
|
p = p * two_to_the_n(lz + 1);
|
|
p = p & vint4(0xFFFF);
|
|
|
|
p = lsr<6>(p);
|
|
|
|
p = p | lsl<10>(vint4(14) - lz);
|
|
|
|
vint4 r = select(p, fp16_one, is_one);
|
|
r = select(r, fp16_small, is_small);
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* @brief Convert 16-bit LNS to float16.
|
|
*/
|
|
static ASTCENC_SIMD_INLINE vint4 lns_to_sf16(vint4 p)
|
|
{
|
|
vint4 mc = p & 0x7FF;
|
|
vint4 ec = lsr<11>(p);
|
|
|
|
vint4 mc_512 = mc * 3;
|
|
vmask4 mask_512 = mc < vint4(512);
|
|
|
|
vint4 mc_1536 = mc * 4 - 512;
|
|
vmask4 mask_1536 = mc < vint4(1536);
|
|
|
|
vint4 mc_else = mc * 5 - 2048;
|
|
|
|
vint4 mt = mc_else;
|
|
mt = select(mt, mc_1536, mask_1536);
|
|
mt = select(mt, mc_512, mask_512);
|
|
|
|
vint4 res = lsl<10>(ec) | lsr<3>(mt);
|
|
return min(res, vint4(0x7BFF));
|
|
}
|
|
|
|
/**
|
|
* @brief Extract mantissa and exponent of a float value.
|
|
*
|
|
* @param a The input value.
|
|
* @param[out] exp The output exponent.
|
|
*
|
|
* @return The mantissa.
|
|
*/
|
|
static ASTCENC_SIMD_INLINE vfloat4 frexp(vfloat4 a, vint4& exp)
|
|
{
|
|
// Interpret the bits as an integer
|
|
vint4 ai = float_as_int(a);
|
|
|
|
// Extract and unbias the exponent
|
|
exp = (lsr<23>(ai) & 0xFF) - 126;
|
|
|
|
// Extract and unbias the mantissa
|
|
vint4 manti = (ai & static_cast<int>(0x807FFFFF)) | 0x3F000000;
|
|
return int_as_float(manti);
|
|
}
|
|
|
|
/**
|
|
* @brief Convert float to 16-bit LNS.
|
|
*/
|
|
static ASTCENC_SIMD_INLINE vfloat4 float_to_lns(vfloat4 a)
|
|
{
|
|
vint4 exp;
|
|
vfloat4 mant = frexp(a, exp);
|
|
|
|
// Do these early before we start messing about ...
|
|
vmask4 mask_underflow_nan = ~(a > vfloat4(1.0f / 67108864.0f));
|
|
vmask4 mask_infinity = a >= vfloat4(65536.0f);
|
|
|
|
// If input is smaller than 2^-14, multiply by 2^25 and don't bias.
|
|
vmask4 exp_lt_m13 = exp < vint4(-13);
|
|
|
|
vfloat4 a1a = a * 33554432.0f;
|
|
vint4 expa = vint4::zero();
|
|
|
|
vfloat4 a1b = (mant - 0.5f) * 4096;
|
|
vint4 expb = exp + 14;
|
|
|
|
a = select(a1b, a1a, exp_lt_m13);
|
|
exp = select(expb, expa, exp_lt_m13);
|
|
|
|
vmask4 a_lt_384 = a < vfloat4(384.0f);
|
|
vmask4 a_lt_1408 = a <= vfloat4(1408.0f);
|
|
|
|
vfloat4 a2a = a * (4.0f / 3.0f);
|
|
vfloat4 a2b = a + 128.0f;
|
|
vfloat4 a2c = (a + 512.0f) * (4.0f / 5.0f);
|
|
|
|
a = a2c;
|
|
a = select(a, a2b, a_lt_1408);
|
|
a = select(a, a2a, a_lt_384);
|
|
|
|
a = a + (int_to_float(exp) * 2048.0f) + 1.0f;
|
|
|
|
a = select(a, vfloat4(65535.0f), mask_infinity);
|
|
a = select(a, vfloat4::zero(), mask_underflow_nan);
|
|
|
|
return a;
|
|
}
|
|
|
|
namespace astc
|
|
{
|
|
|
|
static ASTCENC_SIMD_INLINE float pow(float x, float y)
|
|
{
|
|
return pow(vfloat4(x), vfloat4(y)).lane<0>();
|
|
}
|
|
|
|
}
|
|
|
|
#endif // #ifndef ASTC_VECMATHLIB_H_INCLUDED
|